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| author | Peter Ujfalusi <peter.ujfalusi@linux.intel.com> | 2026-08-05 11:24:13 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-08-05 13:34:36 +0100 |
| commit | e4fe3e046524e5de3c04c6eef3743780cbdc231c (patch) | |
| tree | 5e4b37dfc6b843b67e113012132e8338debfe5b6 /tools/perf/scripts/python/task-analyzer.py | |
| parent | f39a68ed08bb6eef0ae711b41d645ee5e9448c09 (diff) | |
ASoC: cs4265: sort the register default table
reg_defaults must be sorted by ascending register address, as
regcache_lookup_reg() locates entries in it with bsearch(). See commit
fd80df352ba1 ("regcache: Add support for sorting defaults arrays").
cs4265_reg_defaults[] lists CS4265_INT_MASK (0x0e),
CS4265_STATUS_MODE_MSB (0x0f) and CS4265_STATUS_MODE_LSB (0x10) after
CS4265_SPDIF_CTL1 (0x11) and CS4265_SPDIF_CTL2 (0x12), so the binary search
does not find those three entries. regcache_reg_needs_sync() then cannot
compare them against their default and reports that a sync is needed, so
they are written to the device on every regcache_sync() even when they were
never touched.
Sort the table by register address.
Fixes: fb6f806967f6 ("ASoC: Add support for the CS4265 CODEC")
Cc: stable@vger.kernel.org
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://patch.msgid.link/20260805082413.26174-4-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions
