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| author | Md Sadre Alam <md.alam@oss.qualcomm.com> | 2026-08-07 21:33:56 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-08-11 22:14:46 +0100 |
| commit | cdb1dbba490205c32f1e72aaaad26715c8f98f80 (patch) | |
| tree | 28bd0eef91e8f537bbc7c9d71e679d1938b7a5bb /tools/perf/scripts/python/task-analyzer.py | |
| parent | 0d51ff742b416ea42ac36c73c0476f968c1a787a (diff) | |
spi: spi-qpic-snand: add quad mode support
Add support for quad (x4) transfer mode in the QPIC SPI NAND driver.
The controller supports both single (x1) and quad (x4) SPI transfers,
but the driver currently operates only in x1 mode.
Track the QUAD enable state from the device configuration register
(0xB0) and switch the data transfer width accordingly. When the core
enables quad mode, use x4 transfers for read and program operations to
improve throughput.
Introduce a quad_mode flag in struct qpic_spi_nand to cache the current
device state. The flag is updated based on GET_FEATURE responses from
the configuration register.
Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260807-quad-v2-2-8ec821e2f22b@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions