summaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/task-analyzer.py
diff options
context:
space:
mode:
authorJohn Madieu <john.madieu.xa@bp.renesas.com>2026-05-25 11:05:56 +0000
committerGeert Uytterhoeven <geert+renesas@glider.be>2026-06-30 11:52:09 +0200
commitc67b3c631a1bc02dba2c93bcb75eda54b607eae6 (patch)
tree5d41b7c4cb63eb67cb243698219b0d832b687800 /tools/perf/scripts/python/task-analyzer.py
parentdc59e4fea9d83f03bad6bddf3fa2e52491777482 (diff)
dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
RZ/V2H, RZ/V2N, and RZ/G3E support two optional external audio clock inputs (AUDIO_CLKB and AUDIO_CLKC) that can be used by the Audio Clock Generator (ADG) to derive internal audio clocks. The third ADG input (AUDIO_CLKA) is fed internally by the AUDIO_EXTAL pin and does not need a separate binding entry. Update the bindings to allow these optional clocks for all RZ/V2H family SoCs. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260525110603.4018170-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions