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| author | John Madieu <john.madieu.xa@bp.renesas.com> | 2026-05-25 11:05:58 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-07-14 10:36:36 +0200 |
| commit | 35cf35e239477cb28e5f6ccd987933d70c21061f (patch) | |
| tree | 0c9ce298528a23eced3b9bd9c5c12c176a71bde1 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 6fa6ee724d8dadf392139e242ac936b5da730c4b (diff) | |
arm64: dts: renesas: rzv2h: Add audio clock inputs
Model the optional external audio clock inputs as CPG input clocks for
RZ/V2H family SoCs (RZ/V2H, RZ/V2N, RZ/G3E), allowing the Audio Clock
Generator (ADG) to derive internal audio clocks from these external
sources.
The clock frequencies are board-specific and must be overridden in the
board DTS files.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260525110603.4018170-4-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions
