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| author | Bitterblue Smith <rtl8821cerfe2@gmail.com> | 2026-04-19 16:43:53 +0300 |
|---|---|---|
| committer | Ping-Ke Shih <pkshih@realtek.com> | 2026-04-29 11:18:50 +0800 |
| commit | 32cee8a9bb66ceb434b9eae32beb17403287c4d5 (patch) | |
| tree | d63956a6c039feb87c27c457854176c0ff7643c5 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 0df7f0c22d96024f4a9db9f32693c6ea527c0c9d (diff) | |
wifi: rtw89: usb: Enable RX aggregation for RTL8922AU
It uses the same settings as RTL8852CU, but the register and bit names
have "BE" instead of "AX".
Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
Acked-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/bd9e444f-257c-48c8-8adb-f58432b2c5c2@gmail.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions