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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2026-08-13 10:00:24 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-08-14 13:36:56 +0100 |
| commit | 15e9362f6190410557b3d54dae878b061aeab73c (patch) | |
| tree | a2e4e4e58441e589306e80a42c2a9b160c6790e7 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 99542d244f534d4f3af6a76f18c99188458f8d12 (diff) | |
spi: ma35d1-qspi: Add DTR support
The controller has DTR support, a bit must be set for it. The behaviour
is interesting though, as the speed won't improve when enabled. This is
because there seems to be an internal divisor (/2) which keeps the rate
equal when DTR is enabled. As a result, this commit also doubles the
target bus speed, which in practice does not happen. This way, there is
a real gain:
Before:
$ flash_speed /dev/mtd0 -dc10
eraseblock write speed is 1000 KiB/s
[...]
eraseblock read speed is 1199 KiB/s
[...]
After:
$ flash_speed /dev/mtd0 -dc10
eraseblock write speed is 985 KiB/s
[...]
eraseblock read speed is 1540 KiB/s
[...]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20260813-perso-ma35d1-upstream-qspi-v1-4-b217b9870eb1@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions