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| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-02-02 16:07:27 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-02-03 13:47:10 +0530 |
| commit | 0bdd29f5855b54fc4344a3036552f75554ae7573 (patch) | |
| tree | 91c5e37583af4fc6735b8a1d287a41ce87644d40 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 7a687f705e2c62f012d6d803ef86f5bfff41c015 (diff) | |
drm/i915/dp: Refactor dsc_slice_count handling in intel_dp_mode_valid()
Make dsc_slice_count closer to the block where it is used and promote it
from u8 to int. This aligns it with upcoming DSC bubble pixel-rate
adjustments, where the slice count participates in wider arithmetic.
Currently, for non-eDP (DP/DP_MST) cases the slice count is computed only
inside intel_dp_dsc_mode_valid() and is not used by the caller. Once DSC
bubble handling is added, dp_mode_valid() will need access to its own local
slice count for non-eDP cases as well.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260202103731.357416-14-ankit.k.nautiyal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions
