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| author | Jisheng Zhang <jszhang@kernel.org> | 2026-08-03 22:07:27 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-08-04 14:17:32 +0100 |
| commit | 0ab32c1c2b6db53a39c742b9ea5d488dca57cde2 (patch) | |
| tree | 3a275c9ce7c5574e68e31d4150d3b31797f5e0a6 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 63371e187e9d3f7581e81021b9168a6c33cc6c0e (diff) | |
spi: cadence-xspi: only use readsq/writesq under 64BIT
Currently, cadence-xspi depends on 64BIT. This dependency isn't from
cadence xspi controller itself, but from marvell support code and 64bit
slave dma interface performance optimization.
readsq and writesq are only available under 64BIT. For 32BIT platforms,
we can fallback to ioread32_rep/iowrite32_rep. So we can remove another
reason of the 64BIT dependency.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Link: https://patch.msgid.link/20260803140728.12747-4-jszhang@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions
