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| author | Xu Yang <xu.yang_2@nxp.com> | 2026-07-31 16:11:22 +0800 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-08-06 21:15:08 +0530 |
| commit | 01e9e84a43a1b4e9f67b5bd36be3d127d773a223 (patch) | |
| tree | 55710b4e7bfe099e156e26d82b385778303aaa84 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 56eec5d9665cebe580d41cdf2ea7abb52d23e122 (diff) | |
phy: fsl-imx8mq-usb: add control register regmap
The CR port is a simple 16-bit data/address parallel port that is
accessed through 32-bit MMIO registers for on-chip access to the
control registers inside the USB 3.0 femtoPHY. Add control register
regmap and export these registers by debugfs to help PHY's diagnostic.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://patch.msgid.link/20260731-imx8mp-usb-phy-improvement-v8-4-2ec8d6b3854d@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions