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| author | Marek Vasut <marex@nabladev.com> | 2026-04-04 20:35:01 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-04-27 08:31:54 +0900 |
| commit | dc06cf4268a4ad4192fb688ae81c8638df6c8810 (patch) | |
| tree | 471a9d2a5eff7b3e75cba699a1857f3a4d68c259 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 9897a977668121ff9f3e950d9e471011d81c0934 (diff) | |
ASoC: fsl_sai: Add RX/TX BCLK swap support
Add support for setting the Bit Clock Swap bit in CR2 register
via new "fsl,sai-bit-clock-swap" DT property. This bit swaps the
bit clock used by the transmitter or receiver in asynchronous mode,
i.e. makes transmitter use RX_BCLK and TX_SYNC, and vice versa,
makes receiver use TX_BCLK and RX_SYNC.
Signed-off-by: Marek Vasut <marex@nabladev.com>
Link: https://patch.msgid.link/20260404183547.46509-2-marex@nabladev.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions