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authorImre Deak <imre.deak@intel.com>2026-07-14 18:26:57 +0300
committerImre Deak <imre.deak@intel.com>2026-07-20 15:46:58 +0300
commitb03e0f8651ca8d041cb2602be8bb701b5af83dbe (patch)
treedf0bf697b04a71d59b4d580f0428ea295647969e /tools/perf/scripts/python/syscall-counts.py
parenteb23a5abd1d37c25fa906b5116f0814a68f4ee45 (diff)
drm/i915/dp: Enable SST fallback between UHBR and non-UHBR rates
Enable link training fallback between UHBR and non-UHBR link rates on DP SST links. This was disabled so far to preserve the fallback behavior. There isn't a known issue related to such a fallback and DP MST has been using this for a while already. Also, enabling UHBR rates over Thunderbolt tunnels in a follow-up change, which at least on some links supports only 4 lanes and not 1 or 2 lanes on UHBR, makes a UHBR->non-UHBR fallback scenario more likely. At the same time align the corresponding link training fallback kunit test, allowing a UHBR <-> non-UHBR fallback there as well. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.comd> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260714152700.555527-4-imre.deak@intel.com
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