diff options
| author | Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> | 2026-07-08 14:37:12 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-07-15 08:13:13 +0530 |
| commit | 94896bc5fb93d0b18832e5cf00fa5a19f1b5d749 (patch) | |
| tree | 61daed1c15c8d5ac67fcd7b3f0b96f3f65161fe4 /tools/perf/scripts/python/syscall-counts.py | |
| parent | f7768b46b980ba263a39515a8d9e60ef258dc786 (diff) | |
drm/i915/dmc: Enable PIPEDMC_ERROR interrupt on display version 30+
Enable PIPEDMC_ERROR alongside the existing PIPEDMC_GTT_FAULT and
PIPEDMC_ATS_FAULT interrupt bits for display version 30+.
On PTL, DC state transitions do not trigger the spurious PIPEDMC_ERROR
interrupts that were previously a concern. Enable the interrupt so pipe
DMC errors are reported by intel_pipedmc_irq_handler().
v2:
- Remove IGT reference from commit message (Suraj).
Bspec: 70296
Suggested-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260708090712.3800170-1-dibin.moolakadan.subrahmanian@intel.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions