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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2026-03-04 11:33:17 +0000 |
|---|---|---|
| committer | Thomas Gleixner <tglx@kernel.org> | 2026-03-10 18:34:52 +0100 |
| commit | 7585a27644f338b3e764ceeda4be10e7047331a7 (patch) | |
| tree | d54f39cdb5a267622d5eb827c1ae5f72e71806ee /tools/perf/scripts/python/syscall-counts.py | |
| parent | 61adc4813d67990f6f9c20ab8c4a57fb3d969322 (diff) | |
irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger
Handle the RZ/V2H ICU error interrupt to help diagnose latched bus,
ECC RAM, and CA55/IP error conditions.
Support error injection via ICU_SWPE to allow testing the pseudo error
error interrupts.
Account for SoC differences in ECC RAM error register coverage so the
handler only iterates over valid ECC status/clear banks, and route the
RZ/V2N compatible to a probe path with the correct ECC range while
keeping the existing RZ/V2H and RZ/G3E handling.
[ tglx: Convert to hwirq_within() and upgrade to pr_warn() for those errors ]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260304113317.129339-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions