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| author | Anshuman Gupta <anshuman.gupta@intel.com> | 2020-04-15 22:35:52 +0530 |
|---|---|---|
| committer | Uma Shankar <uma.shankar@intel.com> | 2020-04-17 13:12:02 +0530 |
| commit | fc4a8c16e34b2b0a8bd100e1b52dfbba5a8dd981 (patch) | |
| tree | 50361495b9ca19b29dfbd58067584c8715d1b621 /tools/perf/scripts/python/stackcollapse.py | |
| parent | b06ef327e26367b9286a2079b31cde8d2161c0d8 (diff) | |
drm/i915: Power well id for ICL PG3
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200415170555.15531-2-anshuman.gupta@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions