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| author | Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> | 2026-06-30 14:54:01 +0200 |
|---|---|---|
| committer | Linus Walleij <linusw@kernel.org> | 2026-07-01 12:33:18 +0200 |
| commit | e91152802f0d71c14289b1f86d27ec143c49fbdb (patch) | |
| tree | 35755101960b17f26d1ef0c3d681274134023f81 /tools/perf/scripts/python/stackcollapse.py | |
| parent | d10d65d6a2fa0b97f67b8c3ee52303e967b2633c (diff) | |
dt-bindings: pinctrl: s32g2-siul2: describe GPIO and EIRQ resources
Extend the S32G2 SIUL2 pinctrl binding to describe the GPIO data and
external interrupt resources present in the same SIUL2 hardware block.
Besides the MSCR and IMCR registers used for pin multiplexing and pad
configuration, SIUL2 also contains PGPDO and PGPDI registers
for GPIO data and EIRQ registers for external interrupt control.
Add GPIO controller properties because the SIUL2 block also provides
GPIO functionality, and gpio-ranges are needed to describe the
mapping between GPIO lines and pin controller pins.
Document the interrupt controller properties. The SIUL2 block
contains EIRQ hardware as part of the same register space. IRQ support
itself will be added in a follow-up patch series.
Update the example accordingly to show the complete SIUL2 register
layout, including the GPIO data and EIRQ register windows.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
