diff options
| author | Stefano Radaelli <stefano.r@variscite.com> | 2026-06-08 16:41:07 +0200 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-06-29 15:16:36 -0400 |
| commit | dd7858bbdfa84beddf7d08bb82eacc8010221493 (patch) | |
| tree | 9065d3855261197370916f9ddd470a79762ec8d8 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 47f8149d31535adafff43ff23084a97600686ddd (diff) | |
arm64: dts: imx8mp-var-som-symphony: enable PCIe
Add the PCIe reference clock and enable the PCIe controller and PHY on
the Symphony carrier board.
Describe the PERST# reset GPIO and configure the PHY to use an external
reference clock input.
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions