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| author | Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> | 2025-04-11 19:05:31 +0200 |
|---|---|---|
| committer | Hans Verkuil <hverkuil@xs4all.nl> | 2025-04-23 10:55:53 +0200 |
| commit | d71be5add2f3fd4e11c11a21855df17c48088fc2 (patch) | |
| tree | a5159b747f17548cbc7eb242c7b6f46427309d6c /tools/perf/scripts/python/stackcollapse.py | |
| parent | f1c83d2f2841e99f884104e912aa20fcc32b9c2d (diff) | |
media: dt-bindings: renesas,rzg2l-cru: Document Renesas RZ/G3E SoC
The CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC has five
interrupts:
- image_conv: image_conv irq
- axi_mst_err: AXI master error level irq
- vd_addr_wend: Video data AXI master addr 0 write end irq
- sd_addr_wend: Statistics data AXI master addr 0 write end irq
- vsd_addr_wend: Video statistics data AXI master addr 0 write end irq
This IP has only one input port 'port@1' similar to the RZ/G2UL CRU.
Document the CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/r/20250411170624.472257-4-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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