diff options
| author | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2025-03-14 23:35:59 +0000 |
|---|---|---|
| committer | Hans Verkuil <hverkuil@xs4all.nl> | 2025-04-11 13:29:06 +0200 |
| commit | b8f781596da0e540797557c570163b5da0042070 (patch) | |
| tree | ad83f45c00697f4f7cd753d3784e80285eb0cb38 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 88655d64210e36c926d9c8a2617ad97e0bc7a4ad (diff) | |
media: qcom: camss: csiphy-3ph: Add 4nm CSIPHY 2ph 5Gbps DPHY v2.1.2 init sequence
For various SoC skews at 4nm CSIPHY 2.1.2 is used. Add in the init sequence
with base control reg offset of 0x1000.
This initial version will support X1E80100. Take the silicon verification
PHY init parameters as a first/best guess pass.
SKEW_CAL is included as received from the qcom silicon init sequence.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions