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| author | Animesh Manna <animesh.manna@intel.com> | 2026-06-16 01:33:19 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2026-06-16 16:09:52 +0530 |
| commit | b5cbe1aefe9c77f57ede7361dad76854b3118966 (patch) | |
| tree | 73ba836ababf262236f8a057e1343496d06cfeb2 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 21ebf55d694f4d521849d936e3bd8b6e599a85d1 (diff) | |
drm/i915/cmtg: Set CMTG clock select
Program the CMTG Clock Select register based on the transcoder used.
v2:
- Correct mask for PHY B. [Jani]
- Use REG_FIELD_PREP() for enable value. [Dibin]
- Extend cmtg clock select for xe3plpd. [Dibin]
v3:
- CMTG support removed for old platform.
v4:
- Optimize further with else-if. [Uma]
- Correct CMTG_CLK_SEL_B_MASK. [Uma]
v5:
- Add transcoder-port compatibility check. [Dibin]
Bspec: 69103
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Link: https://patch.msgid.link/20260615200339.885190-3-animesh.manna@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions