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authorRuthuvikas Ravikumar <ruthuvikas.ravikumar@intel.com>2023-11-17 03:21:52 +0530
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-21 11:44:52 -0500
commita6a4ea6d7d37cea9132e67a4d3321a455a6b0736 (patch)
tree65b183598d800dc1a9cb60aa751897438ac94565 /tools/perf/scripts/python/stackcollapse.py
parent1d425066f15faa6965fa6361da4c52e4020fd8d0 (diff)
drm/xe: Add mocs kunit
This kunit verifies the hardware values of mocs and l3cc registers with the KMD programmed values. v14: Fix CHECK. v13: Remove ret after forcewake. v11: Add KUNIT_ASSERT_EQ_MSG for Forcewake. v9/v10: Add Forcewake Fail. v8: Remove xe_bo.h and xe_pm.h Remove mocs and l3cc from live_mocs. Pull debug and err msg for mocs/l3cc out of if else block. Add HAS_LNCF_MOCS. v7: correct checkpath v6: Change ssize_t type. Change forcewake domain to XE_FW_GT. Update change of MOCS registers are multicast on Xe_HP and beyond patch. v5: Release forcewake. Remove single statement braces. Fix debug statements. v4: Drop stratch and vaddr. Fix debug statements. Fix indentation. v3: Fix checkpath. v2: Fix checkpath. Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Cc: Mathew D Roper <matthew.d.roper@intel.com> Reviewed-by: Mathew D Roper <matthew.d.roper@intel.com> Signed-off-by: Ruthuvikas Ravikumar <ruthuvikas.ravikumar@intel.com> Link: https://lore.kernel.org/r/20231116215152.2248859-1-ruthuvikas.ravikumar@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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