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| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2021-06-16 17:11:12 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-07-08 15:15:03 -0400 |
| commit | 9cb2f2df669ec7abd9c4421fe8af6e50e920d5bf (patch) | |
| tree | 9ff10dd1729234b8f9607ff0c4bfd2455ad788bf /tools/perf/scripts/python/stackcollapse.py | |
| parent | 46db138dc83ae16e188038358c925c560110f804 (diff) | |
drm/amd/display: Fix updating infoframe for DCN3.1 eDP
[Why]
We're only treating TMDS as a valid target for infoframe updates which
results in PSR being unable to transition from state 4 to state 5.
[How]
Also allow infoframe updates for DCN3.1 - following how we handle
this path for earlier ASIC as well.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions