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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-03-25 19:24:30 +0000 |
|---|---|---|
| committer | Thomas Gleixner <tglx@kernel.org> | 2026-03-26 16:56:23 +0100 |
| commit | 98b24d39c852d2498aae24c9aa0a3b11edb8cc2c (patch) | |
| tree | 3569d3072e61f4bc5ab73435e0750c0e21c6df3c /tools/perf/scripts/python/stackcollapse.py | |
| parent | f9544cad3600f251a7d24c2fb77e7f2abdceb42e (diff) | |
irqchip/renesas-rzg2l: Add RZ/G3L support
The IRQC block on the RZ/G3L SoC is almost identical to the one found on
the RZ/G2L SoC, with the following differences:
- The number of GPIO interrupts for TINT selection is 113 instead of 123.
- The pin index and TINT selection index are not in the 1:1 map.
- The number of external interrupts are 16 instead of 8, out of these
8 external interrupts are shared with TINT.
Add support for the RZ/G3L driver by filling the rzg2l_hw_info table and
adding LUT for mapping between pin index and TINT selection index.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260325192451.172562-16-biju.das.jz@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions