diff options
| author | Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> | 2026-06-16 01:33:35 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2026-06-16 17:20:52 +0530 |
| commit | 9570e945f2b6c9cc39b707022185110d957d4499 (patch) | |
| tree | d846b3daffbc33560f678586b58f9e1eefce89d3 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 3bb44e8d421a1134bb8a9e13061dddd038c0d193 (diff) | |
drm/i915/cmtg: Add CMTG HWGB programming
Program CMTG guardband to generate the Lower/Upper and early entry
guardband indicators to the DMC for DC3co control.
v2:
- Specify the unit for DC3CO entry/exit latency. [Uma]
- Add code comment for default line_time_us. [Uma]
Bspec: 75253
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260615200339.885190-19-animesh.manna@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions