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| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-07-01 14:45:03 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-07-02 09:19:23 +0530 |
| commit | 8e27f752037e72ccee9c4a7c4a6202ecf3daf603 (patch) | |
| tree | 07a0eea472d326bc0f149ceb5ebc8a89661cab72 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 2c9a89d6855c85062350b8a345339e6ffdb25e32 (diff) | |
drm/i915/ltphy: Fix SSC Enablement bit in PORT_CLOCK_CTL
According to Bspec we only need to write SSC Enable PLL A bit
and leave PLL B bit alone in PORT_CLOCK_CTL register.
Bspec: 74667, 74492
Fixes: 3383ba2479f7 ("drm/i915/ltphy: Enable SSC during port clock programming")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260701091503.1302226-3-suraj.kandpal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions