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authorJames Lin <PingLei.Lin@amd.com>2026-06-16 15:33:20 +0800
committerAlex Deucher <alexander.deucher@amd.com>2026-07-01 11:31:40 -0400
commit829769f1cfe88f35125e0fd1186fce5c2aa19a3d (patch)
treed7cd0f841acde7c128fe9f86b8532df539ba497f /tools/perf/scripts/python/stackcollapse.py
parent418755e47af3d280750592cde008d91f5e110126 (diff)
drm/amd/display: scale plane global alpha to 12 bits on DCN 4.2
[why] On DCN 4.2 the global alpha is reported using 12 bits (MPCC_GLOBAL_ALPHA spans bits [0:11]), whereas other ASICs such as DCN 3.1.4 use an 8-bit field (MPCC_GLOBAL_ALPHA spans bits [16:23]). The DRM plane alpha property is 16-bit and amdgpu_dm unconditionally scaled it down by >> 8, which only matches the 8-bit hardware field. On DCN 4.2 this fed a value that was 4 bits too small into the 12-bit field, so the hardware applied the wrong global alpha and the resulting blended output did not match the expected hw * alpha value. [how] Detect DCN 4.2 via amdgpu_ip_version(adev, DCE_HWIP, 0) and scale the 16-bit plane alpha by >> 4 to fill the 12-bit MPCC_GLOBAL_ALPHA field. All other ASICs keep the existing >> 8 behavior for their 8-bit field. Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com> Signed-off-by: James Lin <PingLei.Lin@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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