diff options
| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2023-08-28 11:12:54 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2023-09-05 14:39:18 +0530 |
| commit | 76342fce58a58e3c8326a870adfb6b435ecd9abb (patch) | |
| tree | cdf9409b1cb12e4c7389f2a64fbe8d04b1ff9ed8 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 1bb2af547a4bc2e053b398573d8ec7c3bf5ce69e (diff) | |
drm/i915/vdsc: Refactor dsc register field macro
This patch refactors dsc register related macros that prepares
the values to be written in the register. The current bit shifting
looks bad and going forward will not serve our purpose to readout
dsc register field values the change was suggested by Jani Nikula.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions