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| author | Vitaly Lubart <vitaly.lubart@intel.com> | 2023-08-28 13:07:07 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:42:59 -0500 |
| commit | 5120243bfb0dabc9f16924a5fc66e8ef26f0f8d3 (patch) | |
| tree | 0a22d4ac82c5ad980ef41c0bdde704c1e1059f5f /tools/perf/scripts/python/stackcollapse.py | |
| parent | cd0adf746527dc2d1410adf5bf09ee6f4cd22a79 (diff) | |
drm/xe/gsc: add HECI2 register offsets
Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions