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| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-06-17 10:44:17 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-06-19 10:55:07 +0530 |
| commit | 4a68c7516c57a3d03b406c8aaa073c62149aad68 (patch) | |
| tree | 8f7a8ed0028bb81eff230df8944a7832e37b644d /tools/perf/scripts/python/stackcollapse.py | |
| parent | f7140c7cef3037f5d3757bb5db0f4c6aee4a240f (diff) | |
drm/i915/dsb: Use safe window path when VRR TG is used
When the VRR timing generator is always used, the hardware behaves
as VRR-active regardless of crtc_state->vrr.enable.
The DSB paths that depend on the VRR safe window therefore need to follow
the VRR code paths in that case too:
- dsb_chicken(): program the SAFE_WINDOW chicken bits,
- intel_dsb_vblank_evade(): use vmin/vmax vblank starts for the
wait window,
- intel_dsb_wait_for_delayed_vblank(): wait inside the vmin safe window
before the scanline-based delayed vblank wait.
Introduce helper pre_commit_use_safe_window() and use it in the three sites
v2: Instead of modifying pre_commit_is_vrr_active() use a new helper and
use it only in the required places. (Ville).
v3: -Keep using pre_commit_is_vrr_active() for DCB path. (Ville)
-Add a separate check for fixed RR with VRR TG and use
fixed mode vblank start there. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260617051417.2223526-1-ankit.k.nautiyal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
