diff options
| author | Animesh Manna <animesh.manna@intel.com> | 2026-06-16 01:33:39 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2026-06-16 17:21:15 +0530 |
| commit | 481fe84b7361b3079ce279f7f93f39b9ee88fea9 (patch) | |
| tree | e3f86b02a794b000bd7e415efddfd58c25e13289 /tools/perf/scripts/python/stackcollapse.py | |
| parent | f9360ef0547de02d8e93aa39a9f2c837b73f5291 (diff) | |
drm/i915/cmtg: Add CMTG interrupt handling
Add support for the CMTG vblank interrupt, which is delivered
through the DE port interrupt block. Enable/disable the interrupt
via the DE port IMR around CMTG enable/disable, and dispatch the
CMTG_VBLANK_{A,B} bits to the corresponding pipe vblank handler in
the gen8 DE IRQ handler.
Wired up for DISPLAY_VER 35. The CMTG interrupt is not enabled via
IER today because CMTG is brought up together with the eDP
transcoder; this can be revisited later.
v2:
- Use consistent DC3co check as used in earlier patches. [Uma]
- Use else-if instead of separate if block. [Uma]
- Merge mask and unmask function as it is similar. [Uma]
- Modify DISPLAY_VER() check. [Uma]
v3:
- Enable only vblank interrupt. [Dibin]
v4:
- Keep irq related code to intel_display_irq.c. [Jani, Uma]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260615200339.885190-23-animesh.manna@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
