diff options
| author | Joe Sandom <jsandom@axon.com> | 2026-04-20 10:13:13 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-07-02 14:31:22 -0500 |
| commit | 347318325974e888dc18d9fd15dcc48f671886c9 (patch) | |
| tree | ac55d479a7bba997d23577de905abfaff2ef1d7b /tools/perf/scripts/python/stackcollapse.py | |
| parent | 4c53f51b442ae8cc4545fc5ec349ce6ed7afb4cf (diff) | |
arm64: dts: qcom: sm8550: add PCIe MHI register regions
Add the MHI register regions to the pcie0 and pcie1 controller nodes
to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2)
via debugfs. The PCIe host driver uses this region to read the
link_transition_count from the MHI registers.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Joe Sandom <jsandom@axon.com>
Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-1-b461909c2de8@axon.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions