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authorDamon Ding <damon.ding@rock-chips.com>2026-06-23 15:52:07 +0800
committerHeiko Stuebner <heiko@sntech.de>2026-07-03 18:54:34 +0200
commit337038d31c59d405b89efa7b28fd230273f997ad (patch)
tree1b80a4f8f2667be6f240fdae7020b62cf415e5d1 /tools/perf/scripts/python/stackcollapse.py
parent903f8773ee96c5dc5fb9aec65227f39fd3e7a1dc (diff)
drm/bridge: analogix_dp: Apply standard DP training delay helpers
Replace hardcoded fixed usleep_range() delays during clock recovery and channel equalization with drm_dp_link_train_clock_recovery_delay() and drm_dp_link_train_channel_eq_delay() helpers. The original fixed delays are only valid for the case where bit[6:0] of DPCD TRAINING_AUX_RD_INTERVAL(0000Eh) is 0x00, while core helpers apply spec-compliant timings matching actual receiver capability values. Additionally, add dpcd buffer to struct analogix_dp_device to cache receiver capabilities. Call drm_dp_read_dpcd_caps() at commit entry to populate cached DPCD data for subsequent link training steps, and prepare for further usage of other DP helper APIs. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Tested-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20260623075207.320603-1-damon.ding@rock-chips.com
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