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| author | Charlene Liu <Charlene.Liu@amd.com> | 2026-03-02 15:45:41 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-03-23 14:11:03 -0400 |
| commit | 31ea7b0ef35e6d986cbff2a59e8f3d2cd2ae3810 (patch) | |
| tree | 2ce347cb73305f4218ea2031825528a94ca67f2e /tools/perf/scripts/python/stackcollapse.py | |
| parent | 71488869d933b49d4a7d4b2b20448b6f285327bb (diff) | |
drm/amd/display: dcn42 don't round up disclk and dppclk
[why]
dml2 based on num_enabled clock != 2 to do clock ramming to dpm.
apu has 8 levels dispclk/dppclk/dcfclk/fclk, but only 4 levels of memclk.
to avoid mapping dispclk/dppclk to DPM clock,
based on arch review, force dispclk/dppclk num_level as 2.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions