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authorDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2026-08-07 01:05:51 +0300
committerLinus Walleij <linusw@kernel.org>2026-08-07 20:39:48 +0200
commit239fd71600c5a5ed27980a7d0275706c94eb28bd (patch)
tree769951374dd9454fffd170ce29ce3c2f24f477b7 /tools/perf/scripts/python/stackcollapse.py
parent0562b05f4ac71cc32fce361425c01a6acecec1a0 (diff)
pinctrl: airoha: fix AN7583 MDIO pin mux config
an7583_mdio_pins[] pointed at pins 43/44 (I2C1_SDA/I2C1_SCL) instead of pins 53/54 (MDC_0/MDIO_0 respectively GPIO 51/52). Also the MDIO function group wrote GPIO_SGMII_MDIO_MODE_MASK (bit 13 of REG_GPIO_PON_MODE, an unrelated SGMII MDIO mode) and GPIO_MDC_IO_MASTER_MODE_MODE (BIT(14), an EN7581 specific bit from REG_GPIO_2ND_I2C_MODE). Fix both by setting an7583_mdio_pins[] to { 53, 54 } and rewriting the function group to clear AN7583_MDC_0_GPIO_MODE_MASK (bit 25) and AN7583_MDIO_0_GPIO_MODE_MASK (bit 26) of REG_GPIO_PON_MODE. Both bits are cleared by the hwinit at probe. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
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