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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-06-23 00:35:59 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-06-24 18:54:10 +0300 |
| commit | 230149760cdbc89d450fc7c3aa270811a60ea6d2 (patch) | |
| tree | f63f4d46459699a8cd66951d723b0c8f58b56d60 /tools/perf/scripts/python/stackcollapse.py | |
| parent | d392b88dce93ae1a88d932c8f6680be598d22cd5 (diff) | |
drm/modes: Add DRM_MODE_MATCH_TIMINGS_VRR
Add a new mode matching flag DRM_MODE_MATCH_TIMINGS_VRR. This is
identical to DRM_MODE_MATCH_TIMINGS, except it requires the vsync
pulse to remain anchored to the end of vtotal, as opposed to the
start of the frame. VRR capable hardware can therefore treat
matching modes as just variants of the same mode with a different
vblank lengths.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260622213602.7244-3-ville.syrjala@linux.intel.com
Tested-by: Vidya Srinivas <vidya.srinivas@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions