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| author | Abel Vesa <abel.vesa@oss.qualcomm.com> | 2026-07-09 12:12:11 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-07-15 15:13:37 -0500 |
| commit | e78c2cf207c1ebf4558b709308199ee21de478ac (patch) | |
| tree | 801daf3435c769e00f751ffc77a29f0125db969a /tools/perf/scripts/python/parallel-perf.py | |
| parent | 29019077c414391ff3662710fe7d91740d3d5613 (diff) | |
arm64: dts: qcom: eliza: Enable first QUPv3 wrapper by default
Since each serial engine will be enabled as needed in each board dts,
there is no point of disabling the first QUPv3 wrapper in SoC dtsi.
So enable it by default. This is also now in line with the other SoCs, and
also with the second QUPv3 wrapper.
Fixes: 844807e1f89d ("arm64: dts: qcom: eliza: Add QUPv3, GPI DMA, SDHCI and LLCC nodes")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260709-dts-qcom-eliza-enable-qupv3-1st-v1-1-e9a6904d0dea@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions