diff options
| author | William Palacek <William.Palacek@amd.com> | 2026-07-20 11:47:36 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-07-28 19:17:33 -0400 |
| commit | e3fcdd6194264dda91978a1c97984f83c4e86dfc (patch) | |
| tree | 933fd7fe9b056f6b18cbc002f00d723fa7d7db00 /tools/perf/scripts/python/parallel-perf.py | |
| parent | a5be7ad8f5f0e067613e9197638f216f46252946 (diff) | |
drm/amdkfd: allow CWSR grace period of 0 on supported firmware
The debugger sets the CWSR grace period via AMDKFD_IOC_DBG_TRAP and may
request a value of 0. An earlier change clamped 0 to 1 unconditionally
because most firmware revisions locked up when given an infinite (0)
grace period.
Firmware has since been fixed on most ASICs, so gate the clamp on ASIC
type and MEC firmware version and allow 0 where the running firmware is
known to handle it. Navi3x and MI350 support 0 in every firmware
revision and need no version check. MI100 never received the firmware
fix and is kept clamped. Any unlisted or future ASIC defaults to the
safe (clamped) behaviour.
Signed-off-by: William Palacek <William.Palacek@amd.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions