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authorGuenter Roeck <linux@roeck-us.net>2026-07-27 13:13:54 -0700
committerGuenter Roeck <linux@roeck-us.net>2026-07-27 14:33:23 -0700
commita60f58eb70e4e4c2ba4ace8b292dea64e5b7b290 (patch)
tree0b113e232f4bde8fb1e6c96b215fbb2e9325d79e /tools/perf/scripts/python/parallel-perf.py
parent080bbf42faf77e6489ab30d5114c5f8f6ccbb1b8 (diff)
hwmon: (lm63) Mask PWM frequency multiplier to supported bits
Sashiko is concerned that reading a PWM frequency multiplier outside the supported range of [1, 31] might result in bad PWM values written to the chip. Technically, the chip should never return a value with the upper 3 bits set, so this should never happen. However, it is unknown if there are LM63 variants where the upper bits of the register can be written. Mask the register value read from the chip to only accept the lower 5 bit when reading it from the chip to avoid the problem. Reported-by: Sashiko <sashiko-bot@kernel.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
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