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authorCarlos Song <carlos.song@nxp.com>2026-08-03 11:27:05 +0800
committerAndi Shyti <andi.shyti@kernel.org>2026-08-28 03:00:32 +0200
commit27c9445be86b1313746c46d659d3f823a5f7a218 (patch)
tree57e975b54f1439a286b32a972919670b2185e452 /tools/perf/scripts/python/parallel-perf.py
parentf98d4986482151a835b521a734722fe8dc5ca37d (diff)
i2c: imx-lpi2c: avoid accessing target registers on master-only controllers
Not all LPI2C controller instances implement the Target block. Since commit 90311787f483 ("i2c: imx-lpi2c: reset controller in probe stage"), the driver unconditionally resets both the Master and Target blocks during probe. On controllers that do not support target mode, accessing the Target registers triggers an asynchronous SError and prevents the driver from probing successfully. For example on i.MX8QM: SError Interrupt on CPU2, code 0x00000000bf000002 -- SError Hardware name: Freescale i.MX8QM MEK (DT) pc : lpi2c_imx_probe+0x280/0x594 lr : lpi2c_imx_probe+0x224/0x594 Kernel panic - not syncing: Asynchronous SError Interrupt The VERID register is implemented in the Master block and can be safely accessed on all controller variants. Its FEATURE field indicates whether target mode is supported. Read VERID during probe and use it to determine whether the Target block is present. Only access Target registers when target mode is supported and reject target registration requests with -EOPNOTSUPP otherwise. Fixes: 90311787f483 ("i2c: imx-lpi2c: reset controller in probe stage") Signed-off-by: Carlos Song <carlos.song@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20260803032705.2250373-1-carlos.song@oss.nxp.com
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