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| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-06-22 15:47:36 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-06-29 08:12:26 +0530 |
| commit | 4dfcc789a144a21aa9be94f19f928aaa9fdc834d (patch) | |
| tree | c8d869708fed1133869fbd239c8cebb06a736641 /tools/perf/scripts/python/netdev-times.py | |
| parent | 7a1bbc1bf66fa7491a2264959e92b9ba1f506636 (diff) | |
Revert "drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG"
This reverts commit 4f1cab2e4863d96ce13b8d94151f4848e38c3d5b.
Allowing SCL=0 on platforms with always-on VRR timing generator is
causing underruns and other issues on PTL in some cases.
SCL still needs to be non-zero in certain scenarios. Revert for now
until this is better understood.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260622101736.2389991-1-ankit.k.nautiyal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions