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authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>2026-07-28 17:31:45 +0200
committerChun-Kuang Hu <chunkuang.hu@kernel.org>2026-07-29 12:45:27 +0000
commit3e191eddbdcb8bf7beb1e9b58209073bd5450719 (patch)
tree4252e1a34bb896c86b830c22d6d12e88eb3dc667 /tools/perf/scripts/python/mem-phys-addr.py
parentd8a0962d3506f7c9fdc3cc49c81ff0b8ded09f2f (diff)
drm/mediatek: mtk_dsi: Enable HS clock only at pre-enable
Commit 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock during pre-enable") rightfully moves the HS clock enablement to before atomic_enable(), but it's moving it to mtk_dsi_poweron(), which is not only called in the .atomic_pre_enable() callback for the DRM bridge, but also in the MediaTek DRM's .ddp_start() callback, which happens way before the bridge ones. The HS clock enablement should be done at just the right time, otherwise some bridge chips (or some Display Driver ICs) may not work correctly: this is seen at least with a Parade DSI to eDP bridge (PS8640) on the MT8173 Elm Chromebook. This resolves a regression that was seen on the aforementioned machine, which was happening only after a suspend-resume cycle. Cc: <stable@vger.kernel.org> # 7.1.x Fixes: 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock during pre-enable") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Adam Thiede <me@adamthiede.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20260728153145.578404-1-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
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