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| author | Damon Ding <damon.ding@rock-chips.com> | 2026-06-01 14:50:54 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-06-02 22:01:39 +0200 |
| commit | 104f20616d72825fdcf56cfdc5f89f4e96fd8dbe (patch) | |
| tree | 69e7fa1bacc77946b794367707206b8dcde24a30 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 38f41d4e704c2a9bfc025bb17594d53be010a629 (diff) | |
drm/rockchip: analogix_dp: Enable hclk for RK3588
Acquire and enable the HCLK_VO1 bus clock explicitly for RK3588
eDP controller to guarantee register and datapath access.
The clock was previously enabled implicitly via rockchip,vo-grf
phandle reference, which relies on side effect and is fragile.
Fetch optional "hclk" clock in driver to align with updated device
tree binding and keep consistent with hardware clock dependency.
Fixes: 729f8eefdcad ("drm/rockchip: analogix_dp: Add support for RK3588")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20260601065100.1103873-6-damon.ding@rock-chips.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions