drm/i915/power_well: Enable workaround for DSS clock gating issue

Prevent display corruption observed after restart, hotplug, or unplug
operations on Meteor Lake and newer platforms. The issue is caused by
DSS clock gating affecting DSC logic when pipe power wells are disabled.

Apply this WA by disabling DSS clock gating for the affected pipes
before turning off their power wells. This avoids DSC corruption on
external displays.

v2: Use single intel_de_rmw() (Jani)
    Switch to use drm_dbg_kms() instead of drm_printf() (Jani)
    Remove WA number from commit message (Suraj)
    rename dss_clock_gating_enable_disable() to
    dss_pipe_gating_enable_disable();
v3: Do not use open ended display version when checking
    wa (Matt)

WA: 22021048059
BSpec: 690991, 666241
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260202140242.704234-1-mika.kahola@intel.com

0 files changed, 0 insertions, 0 deletions