diff options
| author | Mark Brown <broonie@kernel.org> | 2026-08-05 13:34:37 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-08-05 13:34:37 +0100 |
| commit | 33c5aaf693d3fb78f6b8a9658939b72b7638243d (patch) | |
| tree | 5211c14905fa455c2617cf86012e0ddd4c1356ef /tools/perf/scripts/python/flamegraph.py | |
| parent | 1b0e5c7a4d90a1390616e8264d5ca50f700fde3d (diff) | |
| parent | e4fe3e046524e5de3c04c6eef3743780cbdc231c (diff) | |
ASoC: cs35l41/cs35l45/cs4265: sort the reg_defaults tables
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> says:
reg_defaults must be sorted by ascending register address as
regcache_lookup_reg() locates the entries in it with bsearch(), see commit
fd80df352ba1 ("regcache: Add support for sorting defaults arrays").
These three tables have entries which are out of order, so the binary search
does not find part of them. For those registers regcache_reg_needs_sync()
cannot compare the cached value against the default and reports that a sync
is needed, so they are written to the device on every regcache_sync() even
when they were never touched.
The patches only reorder the existing entries, the text of every entry is
kept verbatim and no default value is changed. Each table was verified by
evaluating the register addresses and replaying lib/bsearch.c on them.
Entries not reachable by the binary search, per table:
cs35l41_reg 2 (of 47)
cs35l45_defaults 36 (of 73)
cs4265_reg_defaults 3 (of 16)
For cs35l45 this is nearly half of the table: the DSP1_RX*_RATE and
DSP1_TX*_RATE registers sit in the middle of it while their addresses are
far above everything else, which cuts the search off from the whole
0x4c40 - 0xf010 range.
Found by an audit of all reg_defaults tables under sound/, the SoundWire
codec drivers are fixed by a separate series.
Link: https://patch.msgid.link/20260805082413.26174-1-peter.ujfalusi@linux.intel.com
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