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| author | Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> | 2026-06-09 16:16:09 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-07-18 17:03:29 -0500 |
| commit | d3ca4252d21ec85ada29689f78d13d4596749e3a (patch) | |
| tree | 05e23c08a48f46a9d5f60f4234f1c4d12f49f84b /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 5d7ebb1f36ad8a51f4e60819a8c5bddf04a8d1a2 (diff) | |
arm64: dts: qcom: glymur: Drop fake PCIe phy 3B
According to user manual / programming guide there is no separate PCIe
phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two
4-lane blocks. This is also visible in memory map, where the 0xf00000
is marked as the main block with additional sub blocks for each 4-lane
phys.
Describing the sub phys without the rest is not correct from hardware
description, even if it works.
Link: https://lore.kernel.org/r/20260420-optimistic-unnatural-stingray-80da35@quoll/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260609141608.354186-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions