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| author | Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> | 2026-04-07 22:15:19 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-07-01 15:40:57 -0500 |
| commit | d291245e2fb1eba55d751f88613a41e292958a96 (patch) | |
| tree | 497565a11d538dac52ab5bd3e43301150dfb7f94 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 4cd774c1feb3f720265c512174c5c3312eca1be2 (diff) | |
arm64: dts: qcom: monaco: Add default GIC address cells
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
monaco.dtsi:2326.4-2329.30: Warning (interrupt_map): /soc@0/pci@1c00000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component 'parent unit address', which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Fixes: 46a7c01e7e9d ("arm64: dts: qcom: qcs8300: enable pcie0")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260407201518.24949-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions