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| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-07-03 08:56:54 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-07-08 16:14:39 +0530 |
| commit | a78d11e7859b87a0058e9b22d93deff17edd1a22 (patch) | |
| tree | 78fa9ca4dc9ff3f5995274353e4077a97d6c180a /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | cd0121502ce61a2efec23fb61b90ffec300be281 (diff) | |
drm/i915/display: Skip TRANS_VTOTAL.Vtotal write on NVL pre-C0
On Nova Lake A/B steppings the GOP breaks DP-Alt / native DP output
when TRANS_VTOTAL.Vtotal is programmed with a non-zero value, and the
initial hardware readout of that field on such systems ends up in
adjusted_mode.crtc_vtotal = 1 -- tripping the DSB scanline WARN in
assert_dsl_ok() during intel_initial_commit.
Keep TRANS_VTOTAL.Vtotal at 0 on Nova Lake pre-C0 (A0..B3) in both
transcoder timing paths, and restore adjusted_mode.crtc_vtotal from
TRANS_VRR_VMIN in intel_vrr_get_config() so downstream state stays
consistent.
Fixes: f26a8df8dff9 ("drm/i915/display: Program TRANS_VTOTAL from mode vtotal")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260703032653.2122784-1-suraj.kandpal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions