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| author | Ashish Mhetre <amhetre@nvidia.com> | 2026-06-22 06:54:09 +0000 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2026-07-16 23:46:35 +0200 |
| commit | 85220be437fa0cf8515a172848ca71fc298dfde7 (patch) | |
| tree | e031bcacb7d65dca9fc7b8e8c174c1593f13dbad /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | dc59e4fea9d83f03bad6bddf3fa2e52491777482 (diff) | |
dt-bindings: iommu: Fix interrupt type in example
The CMDQV interrupt on Tegra264 is edge-triggered per the hardware
interrupt documentation, but the binding example describes it as
level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so
that it does not propagate the wrong trigger type.
Fixes: 8a59954192eb ("dt-bindings: iommu: Add NVIDIA Tegra CMDQV support")
Reported-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Nicolin Chen <nicolinc@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions