diff options
| author | Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> | 2026-03-17 13:07:07 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-03-26 09:40:42 -0500 |
| commit | 4559b435f741bb6389a30aa440307729a018ce92 (patch) | |
| tree | 96e663ed40ee79f28b2dac37d18a5a0985b3739d /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 93f823e7d48232e62fb8fb74481696609c90244a (diff) | |
arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
has three downstream ports.Two embedded Ethernet devices are present
on one of the downstream ports. The other downstream ports route to
M.2 E key and PCIe x4 connector respectively. All the ports present
in the node represent the downstream ports and embedded endpoints.
Power to the TC9563 is supplied through two LDO regulators, which
are on by default and are added as fixed regulators. TC9563 can be
configured through I2C.
Since PCIe0 now routes to TC9563 instead of WCN6750, disable the
WCN6750 and WPSS device tree nodes to reflect the actual hardware
configuration and avoid probing issues.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260317-industrial-mezzanine-pcie-v5-1-1358978517fe@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions
