diff options
| author | Ping-Ke Shih <pkshih@realtek.com> | 2026-04-24 15:25:50 +0800 |
|---|---|---|
| committer | Ping-Ke Shih <pkshih@realtek.com> | 2026-04-29 13:44:23 +0800 |
| commit | 329e9fff98f85520843e7d75b7033339e5fb2b7e (patch) | |
| tree | 80cc87c4735b53177f9cb5ba86b7f766fd101274 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 6d88244bb129755acca696f9227200f4a2d106a6 (diff) | |
wifi: rtw89: pci: no need to wait CLK ready for RTL8922DE
The bit is to wait for CLK ready when entering PCIE L1SS. However, a
certain host might not enable CLK for a situation, causing device state
stuck and trigger PCIE SER. Unset this bit as default like earlier chips.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260424072552.59220-2-pkshih@realtek.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions