diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> | 2026-03-13 17:27:13 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-03-26 09:40:39 -0500 |
| commit | 2755bdd02a43c204fb0ca02b93787a863c1cf9d2 (patch) | |
| tree | e651a48740cd9136c6c60a64a5ef014719773867 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 7c302a2a6c1a4644e798ecfc4e72ddc4acec653f (diff) | |
arm64: dts: qcom: sm8750: correct Iris corners for the MXC rail
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always
match the PLL corners on the MXC rail. Correct the performance corners
for the MXC rail following the PLL documentation.
Fixes: c0d11ff90475 ("arm64: dts: qcom: sm8750: Add Iris VPU v3.5")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-6-32a393c25dda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions